Microsoft
Principal Silicon Design Verification Engineer
$143K–$304K
Santa Clara, CA +4 · On-site · Principal · Full-time · Posted Oct 20, 2026
- Location
- Santa Clara, CA
Mountain View, CA
Hillsboro, OR
Austin, TX
Redmond, WA - Experience
- Doctorate and 3+ years, or Master's degree and 6+ years, or Bachelor's degree and 8+ years of technical engineering experience; or equivalent experience. Preferred: 10+ years of pre-silicon validation experience.
- Education
- Doctorate, Master's Degree, or Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field; or equivalent experience.
About the job
Leads pre- and post-silicon verification and validation of complex data-processing ASICs and SoCs for datacenter use.
What you'll do
- Lead functional validation using UVM/C test benches; develop test plans, tests, and validation infrastructure.
- Define testing strategies, run and debug tests, and create stress and performance scenarios; support chip bring-up with test firmware.
- Coordinate with architecture, design, verification, and partner teams; improve validation methods and mentor others.
What they ask for
- Ability to meet required Microsoft Cloud Background Check and applicable security screening requirements.
- Provide citizenship or other qualifying status documentation for export-control eligibility assessment.
Nice to have
- 10+ years in pre-silicon validation delivering high-performance switches, accelerators, CPUs, vector processors, GPUs, or relevant experience.
- Experience with UVM/C verification, networking protocols and devices, complex SoCs, Verilog/System Verilog, UVM test benches, regressions, and coverage goals.
Pay
USD $142,800 - $274,800 per year (base salary); USD $188,000 - $304,200 per year (base salary)
Tools
ASIC, SoC, UVM/C, Verilog, System Verilog, Ethernet, TCP/IP, ROCEv2
Model-written summary · the original posting is authoritative