Microsoft
Principal Silicon Engineer
$143K–$304K
Mountain View, CA +2 · On-site · Principal · Full-time · Posted Oct 23, 2026
- Location
- Mountain View, CA
Raleigh, NC
Hillsboro, OR - Experience
- Required: 3+ years with a doctorate, 6+ years with a master’s, or 8+ years with a bachelor’s; equivalent experience accepted. Preferred: 5+ years with a doctorate, 8+ years with a master’s, or 12+ years with a bachelor’s; equivalent experience accepted. Also preferred: 1+ year leading projects and 8+ years in RTL design/design checks and synthesis/timing/PPA.
- Education
- Doctorate, master’s, or bachelor’s in Electrical Engineering, Computer Engineering, Computer Science, or related field; or equivalent experience.
About the job
Leads microarchitecture and RTL design for silicon blocks and subsystems, drives timing closure and design integration, and improves design automation and execution efficiency.
What you'll do
- Own microarchitecture and RTL design, translating system requirements into hardware implementations.
- Lead design-intent validation and static timing for mixed-signal interfaces, coordinating timing, power, and functional requirements across teams.
- Improve design automation and flows, including AI, constraint checking, and PPA improvements; communicate status and risks to program leadership.
What they ask for
- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years technical engineering experience, or Master’s and 6+ years, or Bachelor’s and 8+ years, or equivalent experience.
- Meet Microsoft, customer, and/or government security screening requirements, including the Microsoft Cloud Background Check.
- Provide proof of citizenship, U.S. residency, or other protected status for export-control eligibility assessment; citizenship/status will be verified.
Nice to have
- 1+ year(s) experience working on or leading projects from beginning-to-end.
- Experience in RTL design and design checks, synthesis, timing constraints, PPA trade-offs, RTL-to-physical-design collateral, static timing analysis, and relevant industry tools.
Pay
USD $142,800 - $274,800 per year (base salary); USD $188,000 - $304,200 per year (base salary)
Tools
RTL, PrimeTime, Genus/DC, Innovus/ICC2, Tcl, Python, UPF, MMMC
AI focus
Contribute to design automation, including leveraging AI, constraint-checking, and flow improvements that enhance execution efficiency and PPA.
Model-written summary · the original posting is authoritative