Drimva

Microsoft

Senior Design Verification Engineer - Fabric Interconnect

$120K–$261K

Raleigh, NC +3 · On-site · Senior · Full-time · Posted Oct 15, 2026

Location
Raleigh, NC
Hillsboro, OR
Mountain View, CA
Austin, TX
Experience
Required: Doctorate + 1+ year, master's + 4+ years, bachelor's + 5+ years, or equivalent experience. Preferred: Doctorate + 3+ years, master's + 6+ years, bachelor's + 8+ years, or equivalent experience.
Education
Doctorate, master's, or bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field; or equivalent experience.

About the job

Leads fabric-interconnect integration verification for Microsoft silicon, developing and running verification environments to validate coherency, PCIe/CXL, and configuration traffic.

What you'll do

  • Lead integration-level verification of Fabric Top, including coherency, PCIe/CXL, and configuration access traffic.
  • Define verification strategies and test plans with partner IP, SOC, and VIP teams; develop UVM/System Verilog environments and debug simulations.
  • Improve verification through automation, formal methods, AI, and tools; coach and mentor others.

What they ask for

  • Doctorate in a related field plus 1+ year of technical engineering experience, or a master's plus 4+ years, or a bachelor's plus 5+ years, or equivalent experience.
  • Meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check.
  • Provide citizenship, U.S. residency, or other protected-status documentation for export-control eligibility assessment.

Nice to have

  • Expertise with CHI and AMBA protocols or fabric interconnects, coherency, virtualization, security, interrupts, PCIe/CXL, or protocol bridges.
  • Experience with UVM, System Verilog, Python, verification leadership, and/or applying generative AI to daily tasks.

Pay

USD $119,800 - $234,700 per year (base pay); USD $160,200 - $261,000 per year (base pay)

Tools

UVM, System Verilog, CHI, PCIe, CXL, AMBA, SVTB, Python

AI focus

Use AI-based approaches and generative AI solutions to support verification work and improve verification efficiency.

Model-written summary · the original posting is authoritative

First seen Oct 16, 2026 · Last verified Nov 5, 2026 (UTC)