Microsoft
Senior Firmware Validation Engineer
$120K–$261K
Redmond, WA +1 · On-site · Senior · Full-time · Posted Nov 2, 2026
- Location
- Redmond, WA
Mountain View, CA - Experience
- Required: Doctorate plus 1+ year, master's plus 4+ years, bachelor's plus 5+ years of technical engineering experience, or equivalent experience. Preferred: 8+ years of professional experience in relevant embedded systems work.
- Education
- Doctorate, master's degree, or bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field; or equivalent experience.
About the job
Validates and debugs server, silicon, and rack firmware and system software, including networking solutions for Azure AI training and inference infrastructure.
What you'll do
- Coordinate system software integration, validation, and debugging across server architecture domains.
- Define and validate networking architectures for AI platforms, partnering across teams from pre-silicon through datacenter deployment.
- Improve validation coverage, automation, and release efficiency; create dashboards to track system health and quality.
What they ask for
- Doctorate in a related field and 1+ year of technical engineering experience, or master's degree and 4+ years, or bachelor's degree and 5+ years, or equivalent experience.
- Meet required Microsoft, customer, and/or government security screening requirements, including the Microsoft Cloud Background Check.
- Provide proof of citizenship, U.S. residency, or other protected status for export-control eligibility assessment.
Nice to have
- 8+ years of professional experience in embedded systems design/development, integration, validation, or system-level debugging.
- Experience with data-center networking, validation automation, firmware testing across hardware environments, production issue triage, or hardware debugging tools.
Pay
USD $119,800 - $234,700 per year (base salary); USD $160,200 - $261,000 per year (base salary)
Tools
SoC FWs, BMC, Rack Manager, Ethernet, JTAG, Oscilloscope, Logic Analyzer, FPGA
AI focus
Defines and validates networking architectures for AI training and inference platforms, including scale-up and scale-out deployments.
Model-written summary · the original posting is authoritative