Senior Logic Design Engineer

What you'll do

• Create and maintain SDC timing constraints, and support Physical Design, STA, and DFT teams from RTL handoff through tape-out.
• Analyze synthesis results, optimize RTL for PPA, and perform design-quality checks including timing closure, lint, CDC, synthesis, and low-power intent.
• Develop and integrate functional-block RTL, automate tasks with scripts, and use AI to improve process and development efficiency.

What they ask for

• Technical engineering experience and a degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent experience.
• Meet Microsoft Cloud Background Check requirements.
• Provide citizenship or residency/protected-status documentation to determine eligibility for access to export-controlled information.

Nice to have

• Experience with static timing analysis, SDC/timing constraints, and synthesis setup, debugging, and quality.
• Knowledge of logic design flows, Verilog/SystemVerilog, front-end tools, clock crossings, UPF, and scripting languages such as Perl, Tcl, or Python.

Pay

USD $119,800 - $234,700 per year (base pay); USD $160,200 - $261,000 per year (base pay)

Tools

SDC, RTL, STA, DFT, UPF, Verilog/System Verilog, Perl, Tcl, Python

AI focus

Use AI to improve efficiency within process and development.