Senior Logic Design Engineer

What you'll do

• Build a PCIe subsystem from multiple IPs and collaborate with architecture and IP providers to meet SoC requirements.
• Refine implementations and perform design-quality checks, including Synthesis, Lint, CDC, RDC, Low Power Intent, and Logic Equivalence.
• Address dataflow, clocking, and timing-critical paths, and automate tasks with scripts.

What they ask for

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field and 1+ year of technical engineering experience; or master's degree in one of these fields and 4+ years; or bachelor's degree in one of these fields and 5+ years; or equivalent experience.
• Ability to meet required Microsoft, customer, and/or government security screening requirements, including the Microsoft Cloud Background Check.
• Must provide citizenship or qualifying residency/protected-status proof for export-control eligibility assessment.

Nice to have

• Experience with high-speed PCIe designs and protocols, interface protocols such as AXI or APB, ARM Fabric IPs, or IPXACT.
• Experience with scripting, EDA tools, UPF, clock-crossing techniques, timing analysis and constraints, and low-power design.

Pay

USD $119,800 - $234,700 per year (base salary); USD $160,200 - $261,000 per year (base salary)

Tools

PCIe, AXI, APB, ARM Fabric IPs, IPXACT, Python, Tcl, Perl