Microsoft
Senior Physical Design Engineer
$120K–$261K
Hillsboro, OR +4 · On-site · Senior · Full-time · Posted Oct 20, 2026
- Location
- Hillsboro, OR
Mountain View, CA
Austin, TX
Raleigh, NC
Redmond, WA - Experience
- Required alternatives: 1+ year with a doctorate, 4+ years with a master's degree, or 5+ years with a bachelor's degree in a listed or related field; OR equivalent experience. Preferred: 7+ years in semiconductor design.
- Education
- Doctorate, master's, or bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field; or equivalent experience.
About the job
Leads physical design implementation of silicon, from synthesis through place-and-route and signoff, while optimizing clock construction and design flows.
What you'll do
- Execute RTL-to-GDS physical design, including clock construction and signoff for timing, physical verification, EMIR, formal equivalence, and low-power verification.
- Explore and improve clock-construction methodologies, tools, flows, and optimization approaches.
- Coordinate with design, CAD, architecture, power and performance, technology, and other partner teams; communicate project status and plans.
What they ask for
- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and 1+ year of technical engineering experience; OR a master's degree in one of those fields and 4+ years; OR a bachelor's degree in one of those fields and 5+ years; OR equivalent experience.
- Pass the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
- Provide citizenship or qualifying status documentation for export-control eligibility; citizenship will be verified with a valid passport, with other documents applicable to lawful permanent residents, refugees, and asylees.
Nice to have
- At least 7 years of semiconductor design experience.
- Production silicon tape-outs in advanced foundry nodes; low-power SoC methodology; PPA trade-off knowledge; or familiarity with clock-construction strategies for high-speed designs.
Pay
USD $119,800 - $234,700 per year (base pay); USD $160,200 - $261,000 per year (base pay, San Francisco Bay area and New York City metropolitan area)
Tools
RTL, GDS, CTS, EMIR, SOC, PPA, synthesis, place-and-route
Model-written summary · the original posting is authoritative