Microsoft
Senior/Principal Power and Signal Integrity Engineer
$120K–$304K
Redmond, WA · On-site · Principal · Full-time · Posted Sep 25, 2026
- Experience
- Required: 1+ year with a doctorate, 4+ years with a master's degree, or 6+ years with a bachelor's degree, in industry or R&D. Preferred: 3+ years with a doctorate, 6+ years with a master's degree, or 8+ years with a bachelor's degree, in industry or R&D; equivalent experience stated for both.
- Education
- Doctorate, master's, or bachelor's degree in Physics, Engineering, or related field; OR equivalent experience.
About the job
Defines and validates power integrity, signal integrity, and electrical isolation for next-generation Cryo-CMOS quantum control systems across silicon, package, board, and system levels.
What you'll do
- Architect power delivery networks and isolation strategies for digital, analog, RF, and qubit-control circuitry.
- Analyze and mitigate noise, electromagnetic coupling, crosstalk, and mixed-signal interference; correlate simulations with lab measurements.
- Lead silicon-package-board co-design and establish validation and signoff methodologies with cross-functional hardware teams.
What they ask for
- Doctorate in Physics, Engineering, or related field and 1+ year of industry or R&D experience; OR Master's degree in a related field and 4+ years; OR Bachelor's degree in a related field and 6+ years; OR equivalent experience.
- Meet Microsoft, customer, and/or government security screening requirements, including a Microsoft Cloud Background Check.
- Provide citizenship or eligible status documentation for export-control access; citizenship will be verified with a valid passport, with other documents accepted for applicable statuses.
- Ability to leverage AI tools and work in an AI-first environment.
Nice to have
- Experience with power integrity and signal integrity in mixed-signal systems and silicon-package-board design.
- Experience with simulation tools, lab characterization, advanced packaging, Cryo-CMOS, quantum hardware, or cross-functional hardware leadership.
Pay
USD $119,800 - $234,700 per year (base salary); USD $160,200 - $261,000 per year (base salary); USD $142,800 - $274,800 per year (base salary); USD $188,000 - $304,200 per year (base salary)
Tools
Cryo-CMOS, ASIC, PCB, Synopsys RaptorX, Ansys HFSS, SIwave, Cadence Clarity, Keysight ADS
AI focus
Use AI tools for performance modeling and analysis, research gathering, and task automation; work in an AI-first environment to accelerate hardware development and discovery.
Model-written summary · the original posting is authoritative