Microsoft
Senior Verification Engineer
$120K–$261K
Redmond, WA +2 · On-site · Senior · Full-time · Posted Oct 20, 2026
- Location
- Redmond, WA
Fort Collins, CO
United States - Experience
- Required: 3+ years with a master's degree, or 5+ years with a bachelor's degree, in technical engineering; or equivalent experience. Preferred: 3+ years with a doctorate, 6+ years with a master's, or 8+ years with a bachelor's; or equivalent experience. Also preferred: 4+ years with UVM/System Verilog.
- Education
- Required: master's or bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent experience. Preferred: doctorate in one of these fields, or the stated master's/bachelor's alternatives, or equivalent experience.
About the job
Verifies complex hardware IP and develops test plans, designs, and tools for next-generation Azure cloud servers and applications.
What you'll do
- Research verification tools, recommend make-versus-buy decisions, and create complex product designs.
- Develop technical solutions, cross-check chip architecture, use performance instrumentation, and write performance simulators.
- Create complex test cases and plans, coordinate project schedules and risks, and develop training and device specifications.
What they ask for
- Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of technical engineering experience; or bachelor's degree in one of these fields and 5+ years; or equivalent experience.
- Ability to meet required Microsoft, customer and/or government security screening requirements, including the Microsoft Cloud Background Check.
Nice to have
- 4+ years of experience in UVM (Universal Verification Methodolgy)/System Verilog.
- Git; scripting languages such as Python, Pearl, Shell or related technologies; knowledge of IP, subsystem, full-chip verification workflows, or ASIC/FPGAs.
Pay
USD $119,800 - $234,700 per year (base salary); USD $160,200 - $261,000 per year (base salary)
Tools
UVM (Universal Verification Methodolgy), System Verilog, Git, Python, Pearl, Shell, ASIC/FPGAs
Model-written summary · the original posting is authoritative