Microsoft
SoC Hardware (Power Management) Validation Engineer
$102K–$219K
Hillsboro, OR · On-site · Full-time · Posted Oct 19, 2026
- Experience
- 1+ year with a relevant master's degree, or 2+ years with a relevant bachelor's degree, or equivalent experience.
- Education
- Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field OR equivalent experience.
About the job
Validates and debugs post-silicon SoC power-management features to improve power efficiency, performance, stability, and product readiness.
What you'll do
- Develop and execute validation strategies, test plans, automation, and debug tools for power-management features.
- Lead silicon bring-up, characterization, root-cause analysis, and power-performance correlation across development milestones.
- Collaborate with design, firmware, verification, software, and platform teams; use post-silicon findings to inform pre-silicon verification.
What they ask for
- Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 1+ year of technical engineering experience; OR bachelor's degree in one of these fields and 2+ years of technical engineering experience; OR equivalent experience.
- Meet Microsoft, customer, and/or government security screening requirements, including the Microsoft Cloud Background Check.
- Provide citizenship, U.S. residency, or other protected-status documentation to assess eligibility for access to export-controlled information.
Nice to have
- Verification, logic development, analog validation, or validation-tools experience on a CPU, SoC, or IP development team.
- Experience in power validation, performance testing and tuning, automation or tools/scripts development, hardware/software debug, or silicon content on emulation or FPGA.
Pay
USD $102,100 - $202,200 per year (base salary); USD $133,800 - $219,200 per year (base salary)
Tools
CPU, SoC, IP, FPGA
Model-written summary · the original posting is authoritative