Drimva

Muon Space

FPGA RF Signal Processing Engineer

$190K–$212K

San Jose, CA +1 · Full-time · Posted Aug 17, 2026

Location
San Jose, CA
San Jose, California, United States
Experience
3+ years of professional experience in FPGA development of RF algorithms and translating prototype algorithms into FPGA implementations.
Education
BS/MS in Electrical Engineering, Computer Engineering, or related field
Visa sponsorship
Requires access to export-controlled information: applicants must be a U.S. person, eligible to access the information without export authorization, or eligible and reasonably likely to obtain required export authorization. The position also requires ability and willingness to obtain and maintain a U.S. security clearance.

About the job

Implements and optimizes FPGA-based RF signal processing algorithms for real-time communications, sensing, and related applications.

What you'll do

  • Implement, simulate, optimize, and integrate RF/DSP algorithms on FPGAs, including porting prototypes to ARM FPGA-SoCs.
  • Collaborate on RF hardware bring-up, calibration, and system integration.
  • Prepare technical documentation, design specifications, and test reports.

What they ask for

  • BS/MS in Electrical Engineering, Computer Engineering, or a related field.
  • 3+ years of professional experience developing FPGA implementations of RF algorithms and translating prototypes into FPGA implementations.
  • Experience with RF digital signal processing techniques in areas such as modulation/demodulation, filtering, channel estimation, synchronization, or spectrum monitoring.
  • Expertise in RTL/HDL (Verilog / System Verilog / VHDL), FPGA architecture, and design flows.

Nice to have

  • Familiarity with Xilinx/AMD RFSoC or MPSoC.
  • Proficiency in C/C++ or Rust for embedded and real-time systems.

Pay

USD $190,000 - $212,000 base salary

Tools

Verilog, System Verilog, VHDL, ARM FPGA-SoCs, Xilinx/AMD RFSoC, MPSoC, C/C++, Rust

Model-written summary · the original posting is authoritative

First seen Oct 29, 2026 · Last verified Nov 5, 2026 (UTC)