Neuralink
Digital IC Design Engineer Intern
South San Francisco, California, United States · Internship · Posted Oct 27, 2025
- Experience
- 2+ years of experience in digital design.
About the job
Design and implement low-power digital hardware for neural-interface SoCs, including architecture, RTL, verification, and system optimization.
What you'll do
- Develop micro-architecture and RTL for low-power processors, accelerators, GPUs, and radio or serial-link MAC/PHY.
- Model and optimize architectures for energy, performance, workloads, and manufacturing variation; perform SoC verification and FPGA emulation.
- Collaborate on hardware/software interfaces and silicon bring-up testing.
What they ask for
- Evidence of exceptional ability in electrical engineering, computer science, or computer engineering.
- Proficient in SystemVerilog, C/C++, and Python.
- Experience with complex digital systems spanning architecture, microarchitecture, and RTL using industry-standard tools.
- Experience designing digital signal-processing pipelines from algorithm to RTL.
Nice to have
- Experience in architecture optimization, complex-system verification or physical design, SoC testing, or logic verification.
- Experience with tool-flow automation, embedded design, processor ISA, compiler back-end, PCB design, or firmware.
Pay
$35/Hr USD (hourly rate; California Hourly Flat Rate)
Tools
SystemVerilog, C/C++, Python, SystemC/C++, UVM, FPGA
Model-written summary · the original posting is authoritative