Neurophos
Design for Test Lead
$225K–$300K
Austin, Texas · On-site · Full-time · Posted Sep 18, 2026
- Experience
- 8 to 15 years in DFT.
About the job
Lead design-for-test architecture, coverage sign-off, and production test planning for Neurophos’s digital ASICs, coordinating with RTL, physical design, analog, operations, and package teams.
What you'll do
- Own DFT architecture, test control, memory test, and wafer- and package-level DFT plans across ASIC devices.
- Build and deploy the DFT flow; assess coverage, develop functional test vectors, and own coverage sign-off.
- Specify analog test requirements and lead handoff to post-silicon and production test programs, including OSAT delivery.
What they ask for
- Hands-on ownership of scan, ATPG, and MBIST.
- Architect-level experience assessing a full-chip digital ASIC, setting DFT strategy, and owning coverage sign-off.
- Experience developing and specifying functional test vectors to augment structural coverage.
- Track record through tapeout on a complex compute ASIC.
Nice to have
- Analog test specification experience.
- Cadence toolchain experience; exposure to silicon photonics test or photonic-component DFT; or experience using AI tooling in DFT flows.
Pay
$225K – $300K USD base salary
Tools
ATPG, MBIST, JTAG, MCM, HBM, HAST, Cadence
AI focus
The company develops silicon-photonic hardware for AI inference. The role may use AI tooling in DFT flows; this is listed as preferred experience.
Model-written summary · the original posting is authoritative