Neurophos
Design Verification Lead
Austin, Texas · On-site · Full-time · Posted Sep 16, 2026
- Experience
- 8 to 15 years in design verification.
About the job
Leads design verification for an electronic IC, from module-level simulation through SoC integration, gate-level signoff, and validation planning, while establishing AI-driven verification methods and building the team.
What you'll do
- Own UVM verification methodology, testbench architecture, and verification plans across design levels.
- Set up and operate emulation, own gate-level simulation, and extend the FPGA-based verification harness.
- Use AI tooling to develop testbenches and assertions based on coverage feedback, and build and lead the verification team.
What they ask for
- 8 to 15 years in design verification, including leading verification on a GPU-class or complex compute ASIC through tapeout.
- Deep expertise in UVM and SystemVerilog, including testbench architecture, formal verification, coverage analysis, and CI/CD methodology.
- Gate-level simulation experience.
- Verification experience on a chip with many independently developed blocks and analog components, including integration of analog models.
Nice to have
- Hands-on emulation experience, Palladium or equivalent.
- Development of analog models using WREAL or equivalent descriptions; FPGA-based verification or prototyping; Cadence toolchain; AI tooling for testbench development and coverage closure; or silicon photonics or optical component verification.
Tools
UVM, SystemVerilog, SDF, Palladium, WREAL, FPGA, Cadence
AI focus
Use AI tooling to generate and iterate on testbenches and assertions, optimizing based on coverage feedback; help advance AI-driven verification flows.
Model-written summary · the original posting is authoritative