Neurophos
Principal SoC Design Engineer / SoC Lead
$225K–$300K
Austin, Texas +1 · On-site · Principal · Full-time · Posted Sep 3, 2026
- Location
- Austin, Texas
Sunnyvale, California - Experience
- Principal-level (or equivalent) technical leadership experience; multiple full-chip tapeouts. No number of years stated.
About the job
Lead integration and architecture of a full chip or major subsystem for high-bandwidth, low-power designs, making cross-domain decisions and helping grow the design organization.
What you'll do
- Own full-chip or major subsystem integration and top-level integration flows.
- Make and coordinate technical decisions across system functionality, DFT, power, timing, and interconnect/data-fabric architecture.
- Hire, mentor, and grow engineers across specialty domains.
What they ask for
- Principal-level or equivalent technical leadership experience at a semiconductor or systems company, with multiple full-chip tapeouts.
- Breadth across design domains, including experience spanning areas such as timing closure and interconnect architecture.
- Deep experience in CPU design or high-speed interconnect/data-fabric design.
- Experience with advanced process nodes, high-bandwidth I/O, and large subsystem or full-chip designs.
Nice to have
- Cadence toolchain experience; familiarity with AI-assisted EDA flows such as Cerebrus.
- Familiarity with AI/ML accelerator or large-scale compute workloads.
Pay
$225K – $300K (base salary)
Tools
Cadence, Cerebrus
AI focus
The role integrates SoCs for AI inference compute; familiarity with AI/ML accelerator workloads and AI-assisted EDA flows is preferred.
Model-written summary · the original posting is authoritative