Nexthop AI
Digital Verification Engineer
Santa Clara, California · Hybrid · Full-time · Posted Jul 22, 2026
- Experience
- 3–7 years of digital verification experience on FPGA or ASIC designs.
- Education
- BS/MS in Electrical Engineering, Computer Engineering, or a related field.
About the job
Own verification environments and test suites for FPGA and ASIC digital subsystems, finding design issues in simulation and supporting hardware bring-up and HW/SW validation.
What you'll do
- Build and maintain reusable testbenches, reference models, directed and constrained-random tests, assertions, and coverage goals.
- Run and debug simulations and automated regressions; triage failures with RTL designers and document verification results.
- Support FPGA and board bring-up, validating interfaces, register maps, and boot sequences with firmware and software teams.
What they ask for
- Proficiency in Verilog; SystemVerilog is strongly preferred.
- Hands-on experience with Modelsim / Questasim and/or NC-Verilog.
- Grounding in verification fundamentals, including testbench construction, constrained-random stimulus, functional / code coverage, and assertions.
Nice to have
- UVM or equivalent structured verification methodology experience.
- Knowledge of RTL design, pipelines, clock-domain crossing, bus / interconnect protocols, HW/SW bring-up, networking / switching datapaths, or high-speed interfaces.
Tools
FPGA, ASIC, Verilog, SystemVerilog, Modelsim / Questasim, NC-Verilog, SVA, UVM
Model-written summary · the original posting is authoritative