NUVACORE
CPU Custom Library and Memory Layout Lead
$200K–$300K
Santa Clara, CA +1 · Hybrid · Full-time · Posted Sep 18, 2026
- Location
- Santa Clara, CA
Austin, TX - Experience
- 12+ years; the posting specifies experience in custom/standard-cell and/or memory layout at advanced CMOS nodes.
- Education
- BS or MS degree
About the job
Leads custom library-cell and memory-array layout for an advanced-node CPU, driving layout closure, PPA and manufacturability improvements, automation, and vendor execution.
What you'll do
- Lead physical layout of custom library cells and memory arrays, including prototyping critical cells.
- Own layout closure from floorplanning and place-and-route through DRC/LVS cleanup and extraction hand-off; partner with design, foundry, CAD, and DFT teams to optimize PPA and validate IP on testchips.
- Define layout methods and automation, and manage external layout vendors and contractors.
What they ask for
- BS or MS degree and 12+ years of experience in custom/standard-cell and/or memory layout at advanced CMOS nodes.
- Hands-on transistor-level layout experience with static circuits, state-retaining elements, and memory arrays at advanced CMOS nodes.
- Knowledge of DRC/LVS/antenna rules, parasitic extraction, industry-standard EDA tools, layout-dependent effects, matching, and symmetry techniques.
- Experience providing layout-driven feedback to foundry partners on PPA, yield, and DRC/PDK improvements.
Nice to have
- Experience with full custom layout flows, scripting/automation, production layouts through tape-out, testchip development, or foundry DTCO.
- Experience with GAA nodes, vendor management, or Agentic AI tools for productivity and automation.
Pay
USD 200,000–300,000 per-year-salary (base salary)
Tools
Virtuoso, Calibre, StarRC, SKILL, Python, Tcl
AI focus
Preferred experience using Agentic AI tools for productivity and automation.
Model-written summary · the original posting is authoritative