NUVACORE
CPU Custom Library Cell Design (IC)
$140K–$250K
Austin, TX +1 · Hybrid · Full-time · Posted Sep 18, 2026
- Location
- Austin, TX
Santa Clara, CA - Experience
- Ideally 12+ years in standard cell and/or custom memory circuit design.
- Education
- BS or MS degree.
About the job
Design and characterize custom CPU library cells and close library IP to meet product PPA targets at advanced process nodes.
What you'll do
- Design and characterize cells such as flip-flops, clock-gating cells, level shifters, and AOI cells; own schematic-to-characterization library IP closure.
- Collaborate with Foundry/PDK, CAD, Physical Design, and DFT teams to benchmark processes, validate test-chip IP, and optimize downstream PPA.
- Drive tools, flows, and methodology, including characterization automation and compiler QA.
What they ask for
- Hands-on transistor-level design of static circuits, state-retaining elements, and custom logic gates at advanced CMOS nodes.
- Proficiency with industry-standard EDA tools for schematic, layout, extraction, and characterization in custom cell or memory workflows.
- Experience giving foundry partners feedback to improve PPA, yield, and PDK revisions.
- Knowledge of STA and Liberty/CCS model correlation, including timing and power characterization for Functional and DFT modes.
Nice to have
- Experience across custom circuit design flow, from architecture and circuit design to automation, characterization, and timing/model generation.
- Experience with PDK device characteristics, PPA-focused standard-cell analysis, or Agentic AI tools.
Pay
USD 140,000–250,000 (per-year-salary) — base salary
Tools
EDA, STA, Liberty/CCS, PDK, DRC/LVS, DFT, Monte Carlo
AI focus
Experience using Agentic AI tools for productivity and automation is preferred.
Model-written summary · the original posting is authoritative