NUVACORE
CPU Physical Design (RTL Feasibility)
$140K–$250K
Austin, TX +2 · Hybrid · Full-time · Posted Sep 18, 2026
- Location
- Austin, TX
Bangalore
Santa Clara, CA - Experience
- 12+ years for Lead roles or 5+ years for Individual Contributor roles in CPU physical design.
- Education
- BS or MS degree
About the job
Leads CPU RTL and micro-architecture feasibility work, providing physical-design feedback and driving timing, power, and area outcomes through to design closure.
What you'll do
- Lead RTL and micro-architecture feasibility studies and provide actionable feedback to design teams.
- Drive timing closure and power optimization for CPU units, including RTL intake and design-readiness standards.
- Collaborate with CPU, circuit, CAD, RTL, micro-architecture, and performance-modeling teams.
What they ask for
- BS or MS degree and the applicable CPU physical-design experience requirement: 12+ years for Lead roles or 5+ years for Individual Contributor roles.
- Strong CPU micro-architecture foundation and experience in CPU RTL feasibility, including RTL synthesis and floor planning.
- Deep expertise in timing analysis and timing ECO; proficiency with Synopsys or Cadence EDA tools for CPU physical design.
- Successful production tape-outs, CPU PPA optimization, end-to-end physical-design closure across sign-off domains, and strong communication skills.
Nice to have
- CPU block ownership from RTL to GDS (tape-out); expertise in PD sign-off methodologies including FEV, VCLP, EM/IR, STA, and EXT.
- Python, Perl, and TCL for automation and flow development; experience using Agentic AI tools for productivity and automation.
Pay
USD 140,000–250,000 (per-year-salary) base salary
Tools
Synopsys, Cadence, Python, Perl, TCL, FEV, VCLP, STA
AI focus
Experience using Agentic AI tools for productivity and automation is preferred.
Model-written summary · the original posting is authoritative