Formal Verification Engineer

What you'll do

• Define verification scope and formal test plans; build assumptions, constraints, assertions, cover properties, and reusable formal models.
• Use model checking, equivalence checking, and abstraction to prove designs and investigate bugs in CPU areas such as cache coherence, memory consistency, and speculative execution.
• Debug counterexamples, collaborate with designers on micro-architecture improvements, and maintain formal automation and shared assertion libraries.

What they ask for

• Degree in Electrical/Computer Engineering, Computer Science, or Mathematics, or equivalent practical experience.
• Design-verification experience with hands-on formal verification: 15+ years for Principal or 4+ years for Senior Engineer.
• Hands-on model checking and/or equivalence checking through proof convergence.
• Strong Verilog/SystemVerilog, assertions or temporal logic, CPU micro-architecture, digital logic, and scripting skills.

Nice to have

• Proficiency with Cadence JasperGold, Synopsys VC Formal, or Siemens Questa Formal.
• Experience with proof closure, CPU formal verification domains, security formal verification, or theorem proving.

Pay

USD 140,000–250,000 (per-year-salary) — base salary

Tools

Verilog, SystemVerilog, Python, TCL, Perl, Cadence JasperGold, Synopsys VC Formal, Siemens Questa Formal

AI focus

The CPU is designed for AI infrastructure and agentic computing; the role verifies the CPU using formal methods.