NUVACORE
Hardware Engineer
$140K–$250K
Santa Clara, CA +2 · Hybrid · Full-time · Posted Oct 15, 2026
- Location
- Santa Clara, CA
Austin, TX
Markham, ON - Experience
- 5+ years of professional experience in high-speed hardware board design; 10+ years is listed as a nice-to-have for data center server architecture experience.
- Education
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field; a master’s degree is preferred.
About the job
Designs and develops high-performance, energy-efficient server boards for data center CPU platforms, from architecture and schematic capture through lab validation and manufacturing support.
What you'll do
- Lead architecture and board design for server motherboards, baseboards, and riser cards; oversee schematic capture, component selection, and PCB layout collaboration.
- Coordinate with silicon, package, SI/PI, thermal, mechanical, and software/firmware teams on high-speed interfaces and power delivery.
- Bring up, debug, and validate prototype boards; prepare manufacturing documentation and support production readiness.
What they ask for
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
- 5+ years of professional experience in high-speed hardware board design.
- Proficiency with schematic capture and PCB layout tools such as Cadence Allegro, Concept HDL, OrCAD, or Altium Designer.
- Direct experience with high-speed interfaces, SI/PI constraints, board-level power distribution, DC-DC converters, multi-phase VRMs, and hands-on hardware debugging.
Nice to have
- Master’s degree in Electrical Engineering or Computer Engineering.
- Experience with data center server architectures, OCP standards, silicon-package-board co-design, SI/PI or thermal simulation, or manufacturing integration.
Pay
USD 140,000–250,000 (per-year-salary) base salary
Tools
PCIe Gen6/Gen7, DDR5/LPDDR6, CXL, Cadence Allegro, Concept HDL, OrCAD, Altium Designer, Ansys (SIwave, HFSS)
AI focus
Designs CPU server hardware for AI infrastructure and agentic computing workloads.
Model-written summary · the original posting is authoritative