NVIDIA
Applied Research Engineer, Chip Design
$192K–$356K
US, CA, Santa Clara · Full-time · Posted Jul 23, 2026
- Experience
- 8+ years of proven industry experience.
- Education
- MS or PhD or equivalent experience in Computer Science, Electrical/Computer Engineering, or a related field.
About the job
Applies LLMs and agentic AI to NVIDIA’s ASIC design workflows, moving research into production to accelerate chip design and verification.
What you'll do
- Apply LLMs, coding agents, and agentic systems to RTL generation, design and formal verification, and PPA prediction and optimization.
- Integrate agents into EDA and validation flows, and build data generation and evaluation methods for reliable automation.
- Collaborate with NVIDIA’s Nemotron team on domain-specific data and model post-training for ASIC design.
What they ask for
- Front-end ASIC expertise in design, verification, and timing, plus project experience applying agentic AI to chip design or optimization.
- Hands-on experience building LLM-based agents or AI tooling used by real users, including evaluation, tool integration, and failure analysis.
- Experience with custom model training, fine-tuning, or post-training over proprietary technical data.
- Experience building and maintaining infrastructure such as Docker, Slurm, or CI/CD.
Pay
192,000 USD - 304,750 USD base salary (Level 4); 224,000 USD - 356,500 USD base salary (Level 5)
Tools
LLMs, RL, RLHF/RLAIF, SFT, RLHF/DPO, Docker, Slurm, CI/CD
AI focus
Applies LLMs, coding agents, and agentic AI to ASIC design, verification, and optimization; develops evaluation and synthetic-data methods; and supports model training and post-training with domain-specific data.
Model-written summary · the original posting is authoritative