NVIDIA
ASIC Design Engineer – Clocks IP
$116K–$218K
US, CA, Santa Clara +1 · Full-time · Posted Oct 6, 2026
- Location
- US, CA, Santa Clara
US, TX, Austin - Experience
- 2+ years of relevant work experience.
- Education
- BS in Electrical Engineering or equivalent experience; MS preferred.
About the job
Architect and implement GPU and CPU clocking designs, collaborating across teams from clock-domain planning through RTL implementation, sign-off, and silicon bring-up.
What you'll do
- Architect clock domains and clocking topologies to meet functional, physical, testing, and PPA requirements.
- Work with physical design, timing, verification, DFT, and other teams to address clocking constraints and deliver RTL information.
- Participate in the ASIC execution cycle, including design implementation, fixes, sign-off checks, and silicon bring-up.
What they ask for
- BS in Electrical Engineering or equivalent experience.
- Deep understanding of logic optimization techniques and PPA trade-offs.
- Experience in RTL design (Verilog), verification, and logic synthesis.
- Strong coding skills in Python or other industry-standard scripting languages.
Nice to have
- MS preferred; experience implementing on-chip clocking networks is a bonus.
- Experience with clock controllers or clock logic design, scalable designs and architecture, or hands-on silicon debug.
Pay
116,000 USD - 189,750 USD base salary (Level 2); 136,000 USD - 218,500 USD base salary (Level 3)
Tools
Verilog, Python
Model-written summary · the original posting is authoritative