Drimva

NVIDIA

ASIC Design Engineer - New College Grad 2027

$100K–$190K

US, CA, Santa Clara · Full-time · Posted Sep 28, 2026

Education
Pursuing or recently completed a BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent experience.

About the job

Implements and verifies high-performance, power- and area-efficient RTL for GPU and SoC designs, from microarchitecture through silicon validation support.

What you'll do

  • Analyze architectural trade-offs and develop microarchitecture and RTL that meet design specifications.
  • Deliver fully verified designs that are clean for synthesis and timing, coordinating with architecture, verification, synthesis, timing, and backend teams.
  • Architect silicon-debug features and support post-silicon validation.

What they ask for

  • Pursuing or recently completed a BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent experience.
  • Knowledge of microarchitecture and RTL development (Verilog).
  • Good understanding of ASIC design flow, including RTL design, verification, logic synthesis, and timing analysis.
  • Required exposure to digital systems, VLSI design, computer architecture, and computer arithmetic.

Nice to have

  • Strong C/C++, Python, or Perl skills.
  • Experience with arbiters, scheduling, synchronization, bus protocols, interconnect networks, or caches.

Pay

100,000 USD - 166,750 USD (base salary, Level 1); 116,000 USD - 189,750 USD (base salary, Level 2)

Tools

Verilog, C/C++, Python, Perl

Model-written summary · the original posting is authoritative

First seen Oct 15, 2026 · Last verified Nov 6, 2026 (UTC)