ASIC Floorplan Design Engineer - New College Grad 2026

What you'll do

• Develop and optimize floorplans during early chip development with architecture, design, physical design, and package teams.
• Lead area reviews and identify opportunities to improve area, interconnect, and floorplanning.
• Resolve timing and routing congestion issues and build or improve tools and infrastructure.

What they ask for

• Master’s degree in Electrical Engineering, Computer Science, or Computer Engineering, or equivalent experience.
• Hardware engineering background concentrated in VLSI and/or Computer Architecture.
• Experience with Verilog, System Verilog, or similar HVL.
• Experience with CAD and physical design methodologies, including floorplanning, power/clock distribution, packaging, P&R, and timing closure; programming experience in Python, Perl, and C/C++.

Nice to have

• Experience driving development of large-scale ASIC floorplans.

Pay

116,000 USD - 189,750 USD (base salary, Level 2); 136,000 USD - 218,500 USD (base salary, Level 3)

Tools

Verilog, System Verilog, Python, Perl, C/C++, CAD, P&R

AI focus

The role designs chips for product areas that include artificial intelligence; the posting does not describe AI-specific job duties. NVIDIA states it uses AI tools in its recruiting processes.