ASIC Physical Design and Timing Engineer - New College Grad 2026

What you'll do

• Drive physical design, timing analysis, and closure at block, cluster, and/or full-chip level.
• Support frontend and backend implementation, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation.
• Collaborate with multiple teams on engineering projects.

What they ask for

• Master's degree or higher in Electrical or Computer Engineering (or equivalent experience).
• Proficiency in Timing and Static Timing Analysis (STA).
• Hands-on experience in full-chip/sub-chip STA and timing convergence, and timing constraints generation and management.
• Expertise with industry standard EDA and timing convergence tools.

Nice to have

• Proven experience in timing convergence for ASICs, CPUs, GPUs or Network processors; knowledge of deep sub-micron process nodes.
• Proficiency in AI/LLM and programming languages; physical design and optimization experience is a plus.

Pay

116,000 USD - 189,750 USD base salary; 136,000 USD - 218,500 USD base salary

Tools

Static Timing Analysis (STA), EDA, AI/LLM

AI focus

The role lists proficiency in AI/LLM as a preferred qualification. NVIDIA also states that it uses AI tools in its recruiting processes.