NVIDIA
ASIC Physical Design Engineer, Netlisting - New College Grad 2026
$116K–$218K
US, CA, Santa Clara +1 · Full-time · Posted Aug 13, 2026
- Location
- US, CA, Santa Clara
US, TX, Austin - Education
- Master's or PhD degree in Electrical or Computer Engineering (or equivalent experience).
About the job
Drive ASIC physical design for CPUs, GPUs, and SoCs, focusing on netlist verification, clock-domain-crossing checks, synthesis, netlist quality, and ECO implementation.
What you'll do
- Perform block-, cluster-, or full-chip physical design, including equivalence checking, asynchronous checks, MTBF analysis, logic synthesis, and netlist quality checks.
- Help generate and implement ECOs.
What they ask for
- Master's or PhD degree in Electrical or Computer Engineering, or equivalent experience.
- Knowledge of logic equivalence checking/formal verification from RTL to tapeout using industry-standard tools.
- Understanding of hardware architecture and hands-on RTL/logic design skills for timing closure.
- Experience with clock-domain-crossing checks and MTBF analysis, logic synthesis, industry-standard EDA tools, and programming or scripting languages.
Nice to have
- Experience with logic synthesis and equivalence checking/formal verification; familiarity with industry tools and flows.
- Strong hands-on debugging and problem-solving skills; experience improving workflows through effective AI utilization.
Pay
116,000 USD - 189,750 USD (base salary, Level 2); 136,000 USD - 218,500 USD (base salary, Level 3)
Tools
Synopsys, Cadence, Perl, TCL, Make, Python
AI focus
The role may involve improving workflows and productivity through effective AI utilization; NVIDIA also uses AI tools in its recruiting processes.
Model-written summary · the original posting is authoritative