NVIDIA
EDA Workflow Optimization Engineer
$152K–$288K
US, CA, Santa Clara +3 · Full-time · Posted Oct 7, 2026
- Location
- US, CA, Santa Clara
US, MA, Westford
US, TX, Austin
US, NC, Durham - Experience
- 5+ years of relevant experience.
- Education
- BS in Computer Science or equivalent experience; MS preferred.
About the job
Optimizes NVIDIA’s chip-design workflows, tools, and infrastructure to improve engineering productivity and support development of next-generation chips.
What you'll do
- Investigate workflow issues and opportunities, and develop metrics to measure performance.
- Develop, test, and deploy tools and infrastructure; optimize workflows’ use of compute and storage.
- Collaborate with chip engineers and other teams to continuously improve the chip development process.
What they ask for
- Strong experience investigating and debugging complex problems in a UNIX engineering environment.
- Hands-on experience with architecture involving storage, networking, or compute; experience with ASIC, VLSI, CAD/EDA, or mixed-signal design workflows; hands-on EDA tool experience.
- UNIX systems programming and automation using Python and/or Shell; authoritative use of UNIX and UNIX utilities.
- Excellent planning and communication skills; experience applying data analysis principles and influencing data-driven decisions.
Nice to have
- MS degree.
- Experience with IBM Spectrum LSF and/or SLURM; GPU-based workloads in batch computing and distributed systems; C/C++, Python, and Perl on UNIX.
Pay
152,000 USD - 241,500 USD (base salary, Level 3); 184,000 USD - 287,500 USD (base salary, Level 4)
Tools
UNIX, Python, Shell, IBM Spectrum LSF, SLURM, C/C++, Perl
AI focus
The role optimizes chip-design workflows and infrastructure; the posting does not specify AI-related job duties. NVIDIA states it uses AI tools in its recruiting processes.
Model-written summary · the original posting is authoritative