NVIDIA
GPU/SOC Low-Power Feature Architect
$168K–$310K
US, CA, Santa Clara +5 · Full-time · Posted Sep 29, 2026
- Location
- US, CA, Santa Clara
US, TX, Austin
US, OR, Hillsboro
US, OR, Remote
US, AZ, Remote
US, CA, Remote - Experience
- Minimum 10 years; the posting lists power management, use case analysis, perf/power modeling, bringup, and/or debug as areas of experience.
- Education
- BS or MS degree in EE/CE or equivalent experience.
About the job
Architects and optimizes power, efficiency, and interoperability for next-generation high-speed I/O interconnects, including NVLink and NVLink-C2C.
What you'll do
- Contribute to high-speed I/O design and optimize power consumption.
- Ensure interoperability across connected devices and complex system topologies; debug high-speed I/O issues.
- Collaborate across engineering teams to drive design, development, debugging, and product release.
What they ask for
- BS or MS degree in EE/CE or equivalent experience.
- Minimum 10 years working on capacity - power management, use case analysis, perf/power modeling, bringup, and/or debug.
- Strong EE fundamentals and knowledge of computer architecture, high-speed interfaces, timing analysis, process variations, statistical error rates, and power analysis.
- Track record of influence, leadership, and collaboration across multiple teams.
Nice to have
- Experience with system-level and interconnect power management optimizations.
- Silicon and platform-level power modeling for active/idle use cases; understanding of firmware/driver structures and their interaction with HW.
Pay
168,000 USD - 264,500 USD base salary (Level 4); 196,000 USD - 310,500 USD base salary (Level 5)
Tools
NVLink, NVLink-C2C
AI focus
The role supports product lines including artificial intelligence. NVIDIA states that it uses AI tools in its recruiting processes.
Model-written summary · the original posting is authoritative