NVIDIA
HSIO Validation Lead – Silicon Co-Design
$168K–$310K
US, CA, Santa Clara · Full-time · Posted Sep 23, 2026
- Experience
- 8+ years; no alternatives stated.
- Education
- BS or MS in Electrical Engineering, Computer Engineering, or Systems Engineering, or equivalent experience in the lab.
About the job
Leads post-silicon validation and debug of high-speed interfaces across NVIDIA GPUs, CPUs, and SoCs, from first power-on through production readiness.
What you'll do
- Own bring-up, characterization, validation, root-cause analysis, and confirmation of fixes for HSIO issues.
- Define validation strategy, including test coverage, debug priorities, margining methodology, and stress criteria.
- Build and direct AI agents and analysis flows for debug triage and data pipelines; drive interoperability and improve future validation methods.
What they ask for
- BS or MS in Electrical Engineering, Computer Engineering, or Systems Engineering, or equivalent experience in the lab.
- 8+ years in silicon validation, HSIO bring-up, or high-speed interface debug on real hardware.
- Deep protocol expertise in PCIe, NVLink, CXL, C2C, Ethernet, USB, or similar high-speed interface technologies.
- Strong signal-integrity fundamentals, hands-on lab depth, and ability to debug across hardware, firmware, drivers, and platform design.
Nice to have
- Built or deployed AI-driven flows for HSIO debug or failure triage.
- Track record solving customer-critical or production-blocking HSIO failures; experience setting technical direction or developing engineers.
Pay
168,000 USD - 264,500 USD base salary (Level 4); 196,000 USD - 310,500 USD base salary (Level 5)
Tools
PCIe, NVLink, C2C, CXL, Ethernet, USB, SERDES, BERTs
AI focus
Own and direct AI agents for automated debug triage, intelligent data pipelines, and analysis flows; assess where AI helps and where it introduces risk.
Model-written summary · the original posting is authoritative