Low Power ASIC Engineer - New College Grad 2027

What you'll do

• Work with Low Power Architecture, Design, and Software teams to understand upcoming features.
• Architect and develop testbenches, verification infrastructure, and test plans for power management solutions.
• Improve power-aware design verification methods and simulation and debug efficiency.

What they ask for

• Recently completed a BS, MS, or PhD in Electrical or Computer Engineering, or equivalent experience.
• Understanding of low-power design techniques and processor architecture, including related power-management design and verification.
• Experience with Incisive Low-Power or Synopsys VCS NLP; strong debugging skills and Verdi experience.
• Fluency in Verilog and SystemVerilog, with understanding of UVM.

Nice to have

• Prior knowledge of Low Power Architecture, Low Power CV, and deep learning; understanding of power intent in UPF format.
• Scripting in Python or PERL; knowledge of C or C++; or experience maintaining simulation-build scripts or Makefiles.

Pay

100,000 USD - 166,750 USD (base salary, Level 1); 116,000 USD - 189,750 USD (base salary, Level 2)

Tools

Incisive Low-Power, Synopsys VCS NLP, Verdi, Verilog, SystemVerilog, UVM, UPF, Python