NVIDIA
Package Design Methodology Engineer
$136K–$264K
US, CA, Santa Clara +2 · Full-time · Posted Oct 12, 2026
- Location
- US, CA, Santa Clara
US, TX, Austin
US, CA, Remote - Experience
- 5+ years of flow and methodology development experience building package-design flows used by engineering teams at scale.
- Education
- BS in Computer Science, Electrical Engineering, or a related field (or equivalent experience).
About the job
Develop and maintain production-grade EDA tools and design flows for constructing, analyzing, and validating NVIDIA silicon and substrate package designs.
What you'll do
- Design and implement VLSI tools for silicon and substrate design.
- Develop maintainable, user-friendly applications and package design flows, tools, and methodologies.
- Optimize package designers’ workflows across stages of production.
What they ask for
- BS in Computer Science, Electrical Engineering, or a related field (or equivalent experience).
- 5+ years of flow and methodology development experience building package-design flows used by engineering teams at scale.
- Programming proficiency in Python and/or C++, including data structures, algorithms, object-oriented design, and code quality practices.
- Demonstrated application of AI/ML techniques in engineering workflows and strong understanding of electrical engineering fundamentals relevant to VLSI package design.
Nice to have
- Understanding of VLSI package design, interposer, and IC physical design.
- Strong expertise developing package design flows and methodologies.
Pay
136,000 USD - 218,500 USD base salary (Level 3); 168,000 USD - 264,500 USD base salary (Level 4)
Tools
Python, C++, EDA
AI focus
Apply AI/ML techniques in engineering workflows, such as using LLMs for code generation and debugging, building ML-assisted design analysis tools, or integrating AI-assisted flows into EDA environments.
Model-written summary · the original posting is authoritative