Principal Solutions Architect – Semiconductor Test

What you'll do

• Set test development strategy and architectural trade-offs across the full test flow; establish guidelines for test programs and ATE platform reuse.
• Partner with engineering and manufacturing teams on DFT architecture and product testability; lead roadmaps and mentor senior engineers.
• Drive AI/ML adoption for yield learning, outlier detection, predictive binning, and test-time optimization; engage with vendors and industry groups.

What they ask for

• 15+ years of hands-on semiconductor test engineering experience in a fab, IDM, or OSAT environment.
• Extensive knowledge in at least three areas: ATE platform architecture, test program development, DFT methodology, yield analysis, or test data/ML analytics.
• Skilled in leading ATE platforms such as Advantest V93000, Teradyne UltraFLEX/ETS, or similar; strong DFT architecture background.
• Proficiency in test-related scripting and automation (Python, Perl, C++, or platform-native languages); ability to lead multi-site, cross-functional initiatives.

Nice to have

• Experience applying ML/AI to yield analysis, PAT/GDBN outlier screening, or adaptive test; knowledge of STDF, ATDF, JMP, or Spotfire.
• Experience with mixed-signal, RF, or high-speed I/O test; advanced packaging, industry standards, or ATE vendor co-development exposure.

Pay

216,000 USD – 345,000 USD base salary

Tools

Advantest V93000, Teradyne UltraFLEX/ETS, Python, Perl, C++, STDF, ATDF, JMP

AI focus

Drive AI/ML techniques for yield learning, outlier detection, predictive binning, and test-time optimization; ML/AI experience in yield analysis, outlier screening, or adaptive test is preferred.