RTL Power Optimization Engineer – New College Grad 2026

What you'll do

• Run pre-silicon power analysis, compare results, and investigate trends and anomalies.
• Apply AI to RTL or architectural power optimization; prototype features in Verilog and analyze their power impact.
• Help architects and RTL designers interpret power data, identify power bugs, and implement fixes.

What they ask for

• Pursuing or recently completed an MS or PhD in Electrical Engineering, Computer Engineering, or a related field, with coursework or experience in AI, Digital Design, and VLSI concepts (or equivalent experience).
• Understanding of RTL power optimization, backend flows, and RTL implementation of low-power techniques and their trade-offs.
• Strong Python programming skills and coursework or hands-on experience in Machine Learning and Artificial Intelligence, including applying ML to EDA and silicon power problems.
• Experience debugging RTL or gate-level power anomalies; strong written and verbal communication skills.

Nice to have

• Exposure to industry power analysis tools such as PowerArtist, PrimeTime PX, or equivalent.

Pay

116,000 USD - 189,750 USD (base salary); 136,000 USD - 218,500 USD (base salary)

Tools

Python, PowerArtist, PrimeTime PX, Verilog

AI focus

Use AI/ML to develop RTL or architectural power optimization solutions and analysis flows for EDA and silicon power problems.