Drimva

NVIDIA

Senior ASIC Design Engineer

$136K–$264K

US, CA, Santa Clara · Senior · Full-time · Posted Oct 15, 2026

Experience
5+ years of relevant / meaningful work experience.
Education
A Bachelors or Masters Degree (or equivalent experience).

About the job

Design and implement verified, high-performance, area- and power-efficient RTL for SoCs and GPUs, including architecture, synthesis, and verification work.

What you'll do

  • Document, implement, and deliver RTL that meets design targets and specifications.
  • Perform architecture and micro-architecture design, RTL design and synthesis, and logic and timing verification.
  • Help define verification scope and infrastructure, and coordinate with ASIC development teams.

What they ask for

  • Bachelor’s or Master’s Degree (or equivalent experience).
  • Proven hardware engineering background focused on VLSI and Computer Architecture.
  • Expertise in Verilog, System Verilog, or similar HDL, and proficiency in Perl/Python or similar scripting languages.
  • Experience with logic synthesis and timing analysis, design and verification tools, and unit- and system-level test bench environments.

Nice to have

  • Experience working on embedded processors.
  • Verification experience using random stimulus, functional coverage, and assertion-based methodologies.

Pay

136,000 USD - 218,500 USD base salary (Level 3); 168,000 USD - 264,500 USD base salary (Level 4)

Tools

Verilog, System Verilog, Perl, Python, VCS, Verdi, GDB

Model-written summary · the original posting is authoritative

First seen Oct 15, 2026 · Last verified Nov 5, 2026 (UTC)