Senior ASIC Design Engineer - Agentic AI

What you'll do

• Document and deliver guidelines for high-performance, power- and area-efficient RTL design.
• Develop agentic AI solutions to craft micro-architecture, implement RTL, and deliver verified, synthesis- and timing-clean designs.
• Collaborate with designers and tool and flow owners; build and deploy LLM-powered engineering assistants and dialogue systems.

What they ask for

• Experience in micro-architecture and RTL development (Verilog) for complex designs, and deep understanding of ASIC design flow.
• Required exposure to digital systems and VLSI design, computer architecture, and computer arithmetic.
• Proficiency in Python prototyping and foundational knowledge of data structures, algorithms, and software engineering principles.
• Experience fine-tuning large language models and building multi-agent systems, RAG pipelines, and vector databases.

Pay

168,000 USD - 264,500 USD base salary (Level 4); 196,000 USD - 310,500 USD base salary (Level 5)

Tools

Verilog, Python, LLM, RAG, vector databases

AI focus

Develop agentic AI for chip design, fine-tune large language models, build multi-agent systems and RAG pipelines, and deploy LLM-powered engineering assistants and multi-turn, multi-modal dialogue systems.