NVIDIA
Senior ASIC Design Engineer - DFT
$168K–$310K
US, CA, Santa Clara · Senior · Full-time · Posted Oct 6, 2026
- Experience
- 8+ years of hands-on experience in SoC architecture, RTL design, and verification.
- Education
- BS/MS Electrical or Computer Engineering (or equivalent experience) in related domain.
About the job
Architects, designs, implements, and verifies DFT IPs for next-generation SoCs, supporting the silicon lifecycle from pre-silicon verification through post-silicon validation.
What you'll do
- Own fuse controller and other DFT IP architecture and design; develop and improve DFT methodologies.
- Coordinate feature definition and IP integration with architecture, platform, software, design, verification, synthesis, timing, and backend teams; create and execute test plans.
- Support post-silicon bring-up, validation, debug, and issue resolution, and mentor junior engineers.
What they ask for
- BS/MS in Electrical or Computer Engineering (or equivalent experience) in a related domain, with proven DFT experience.
- 8+ years of hands-on experience in SoC architecture, RTL design, and verification.
- Experience in DFT design, methodology, and implementation; proficiency in micro-architecture and RTL development using Verilog.
- Post-silicon bring-up experience on ATE, including pattern formats, test program development, and failure analysis; scripting proficiency in Python, Perl, or Tcl.
Nice to have
- UVM-based verification experience.
- Experience designing fuse, eFuse, or on-chip security blocks; track record architecting DFT IPs across multiple product generations.
Pay
168,000 USD - 264,500 USD base salary; 196,000 USD - 310,500 USD base salary
Tools
Verilog, UVM, Python, Perl, Tcl, ATE
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