NVIDIA
Senior ASIC Design Engineer
$168K–$310K
US, CA, Santa Clara · Senior · Full-time · Posted Aug 14, 2026
- Experience
- 8+ years of meaningful work experience.
- Education
- Bachelor’s Degree or equivalent experience in Electrical Engineering, Computer Engineering, or Computer Science.
About the job
Implements and verifies high-performance, power- and area-efficient RTL for GPU and SoC designs, from micro-architecture through synthesis and timing, and supports silicon debug and validation.
What you'll do
- Analyze architectural trade-offs and develop micro-architecture and RTL for GPU IP.
- Deliver fully verified, synthesis- and timing-clean designs in collaboration with architecture, verification, synthesis, timing, and back-end teams.
- Design features for silicon debug and support post-silicon validation.
What they ask for
- Bachelor’s Degree or equivalent experience in Electrical Engineering, Computer Engineering, or Computer Science.
- Experience in micro-architecture and RTL development (Verilog), focused on areas such as arbiters, scheduling, synchronization, bus protocols, interconnect networks, and/or caches.
- Strong understanding of ASIC design flow, including RTL design, verification, logic synthesis, and timing analysis.
- Exposure to digital systems and VLSI design, computer architecture, and computer arithmetic.
Nice to have
- Strong C/C++, Python, or Perl skills.
- Good debugging and analytical skills.
Pay
168,000 USD - 264,500 USD base salary (Level 4); 196,000 USD - 310,500 USD base salary (Level 5)
Tools
Verilog, C/C++, Python, Perl
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