NVIDIA
Senior ASIC Design Engineer - Memory Subsystem
$136K–$264K
US, CA, Santa Clara · Senior · Full-time · Posted Oct 13, 2026
- Experience
- 5+ years of experience.
- Education
- BS or MS in Electrical Engineering or Computer Engineer or related degree (or equivalent experience).
About the job
Designs and delivers memory-subsystem microarchitecture and RTL, including synthesis and timing analysis, in collaboration with architecture, verification, and physical-design teams.
What you'll do
- Collaborate with architecture, design verification, formal verification, and physical design teams.
- Develop microarchitecture and RTL designs for memory-subsystem components.
- Perform synthesis and timing analysis using CAD tools and current process technologies.
What they ask for
- Strong proficiency in Verilog or VHDL.
- Scripting language experience, such as PERL.
- BS or MS in Electrical Engineering, Computer Engineering, or a related degree, or equivalent experience.
Nice to have
- Experience with high-speed coherent interconnects, protocol bridges, hardware-managed coherency, or system-level caches.
- Experience with multiple clock domains and asynchronous interfaces; knowledge of CHI/CXL/PCI-E specifications.
Pay
136,000 USD - 218,500 USD base salary; 168,000 USD - 264,500 USD base salary
Tools
Verilog, VHDL, PERL, CHI, CXL, PCI-E
Model-written summary · the original posting is authoritative