NVIDIA
Senior ASIC Design Verification Engineer - LPU
$168K–$310K
US, CA, Santa Clara +5 · Senior · Full-time · Posted Sep 22, 2026
- Location
- US, CA, Santa Clara
US, MA, Westford
US, TX, Austin
US, NC, Durham
US, CO, Boulder
US, WA, Seattle - Experience
- 8+ years of relevant industry experience.
- Education
- Bachelor’s degree in EE, CS, or CE (or equivalent experience).
About the job
Verifies the design and implementation of an inference accelerator ASIC, including its architecture, reference models, and microarchitecture.
What you'll do
- Define verification scope, build verification infrastructure, and verify design correctness.
- Collaborate with architects, designers, and pre- and post-silicon verification teams.
- Develop and optimize automated verification flows.
What they ask for
- Bachelor’s degree in EE, CS, or CE (or equivalent experience).
- Background building block- and SoC-level testbenches, with strong debugging and analytical skills.
- Experience with random stimulus, functional coverage, and assertion-based verification methodologies and tools.
- Expertise in SystemVerilog and Universal Verification Methodology (UVM); experience with VCS, Verdi, or equivalent.
Nice to have
- Background in UPF power verification or netlist and DFT verification.
- Perl/Python and C/C++ experience.
Pay
168,000 USD - 264,500 USD (base salary, Level 4); 196,000 USD - 310,500 USD (base salary, Level 5)
Tools
SystemVerilog, Universal Verification Methodology (UVM), VCS, Verdi, UPF, Perl/Python, C/C++
AI focus
Knowledge of applying machine learning to ASIC verification flow.
Model-written summary · the original posting is authoritative