NVIDIA
Senior ASIC Floorplan Design Engineer
$196K–$310K
US, CA, Santa Clara +1 · Senior · Full-time · Posted Oct 14, 2026
- Location
- US, CA, Santa Clara
US, TX, Austin - Experience
- 10+ years of experience.
- Education
- MSEE/MSCE (or equivalent experience).
About the job
Design and develop ASIC floorplans for next-generation SoCs, CPUs, and GPUs, balancing area, performance, power, and cost from early architecture through physical design.
What you'll do
- Collaborate with multidisciplinary teams to create chip floorplans optimized for target markets.
- Identify and resolve area, interconnect, timing, and floorplan issues with ASIC and physical design teams.
- Develop AI workflows and productivity tools to improve chip-area optimization and execution speed; identify and mitigate technical and product risks.
What they ask for
- MSEE/MSCE or equivalent experience, with broad and deep chip-development experience.
- Experience developing SoC, CPU, graphics, memory, and I/O subsystems.
- Experience with physical design methodologies, chip floorplanning, power/clock/reset distribution, DFT, place and route, timing closure, and packaging.
- Agentic AI workflows and experience with Python, Perl, and/or C++; strong cross-team communication and technical problem-solving skills.
Nice to have
- Experience developing large-scale ASIC floorplans for chiplet-based SoC and/or CPU projects.
- Strong algorithm development and programming skills; ability to work with incomplete data, evolving requirements, and tight schedules.
Pay
196,000 USD - 310,500 USD (base salary)
Tools
Python, Perl, C++
AI focus
Develop AI workflows and productivity tools to improve chip-area optimization and execution speed; the posting also mentions agentic AI workflows.
Model-written summary · the original posting is authoritative