NVIDIA
Senior ASIC Floorplan Design Engineer
$196K–$368K
US, CA, Santa Clara +1 · Senior · Full-time · Posted May 21, 2026
- Location
- US, CA, Santa Clara
US, TX, Austin - Experience
- 12+ years of relevant work experience.
- Education
- Master’s degree in Electrical Engineering, Computer Science, or Computer Engineering, or equivalent experience.
About the job
Designs and optimizes ASIC floorplans for next-generation SoCs and GPUs, addressing area, timing, and routing challenges and improving design tools and infrastructure.
What you'll do
- Develop and optimize floorplans during early chip development; drive area reviews and identify improvement opportunities.
- Resolve timing and routing congestion issues with physical and ASIC design teams by influencing design and implementation decisions.
- Build tools and improve infrastructure to optimize chip area and execution speed.
What they ask for
- Master’s degree in Electrical Engineering, Computer Science, or Computer Engineering, or equivalent experience.
- Deep hardware engineering background concentrated in VLSI and/or Computer Architecture.
- Experience with Verilog, System Verilog, or similar HVL; CAD and physical design methodologies, including floorplanning, power/clock distribution, packaging, P&R, and timing closure.
- Programming experience in Python, Perl, and C/C++.
Nice to have
- Experience driving development of large-scale ASIC floorplans.
Pay
196,000 USD - 310,500 USD base salary (Level 5); 232,000 USD - 368,000 USD base salary (Level 6)
Tools
Verilog, System Verilog, Python, Perl, C/C++, CAD, P&R
AI focus
The role designs chips for product areas including artificial intelligence; NVIDIA also uses AI tools in its recruiting processes.
Model-written summary · the original posting is authoritative