NVIDIA
Senior ASIC Physical Design Engineer, Cache Coherent Interconnects
$136K–$264K
US, CA, Santa Clara +1 · Senior · Full-time · Posted Aug 10, 2026
- Location
- US, CA, Santa Clara
US, OR, Hillsboro - Experience
- 5+ years of experience in processor or other related high-performance semiconductor designs.
- Education
- Master’s Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience.
About the job
Performs physical design, synthesis, and timing closure for CPU on-chip interconnect networks and last-level caches, helping evaluate next-generation designs.
What you'll do
- Achieve timing, area, performance, and power goals through synthesis and physical design.
- Evaluate physical design for next-generation coherent interconnects and system-level caches.
- Collaborate with logic designers on micro-architecture definition and feasibility.
What they ask for
- Physical design expertise in high-frequency design, including hands-on synthesis, timing analysis, floor-planning, and knowledge of industry-standard physical design tools.
- Strong communication and interpersonal skills, and ability to work in a dynamic, global team.
Nice to have
- Experience in interconnect/cache/core design.
- Verilog expertise and deep understanding of ASIC design flow, including RTL design and verification, DFT, and ECO.
Pay
136,000 USD - 218,500 USD (base salary); 168,000 USD - 264,500 USD (base salary)
Tools
Verilog, RTL, DFT, ECO
Model-written summary · the original posting is authoritative