NVIDIA
Senior ASIC Timing Engineer
$136K–$264K
US, CA, Santa Clara +3 · Senior · Full-time · Posted Oct 5, 2026
- Location
- US, CA, Santa Clara
US, TX, Austin
US, OR, Hillsboro
US, NC, Durham - Experience
- 5 years in Timing and STA with a BS, or 3 years with an MS.
- Education
- BS (or equivalent experience) in Electrical or Computer Engineering, or MS (or equivalent experience).
About the job
Leads timing analysis and closure for NVIDIA GPUs, CPUs, LPUs, and SoCs across block, cluster, and full-chip levels.
What you'll do
- Drive timing analysis and closure, including constraint development, timing and power convergence, and ECO implementation.
- Collaborate with RTL, DFX, Clocks, and methodology teams on closure strategies and flow improvements.
- Analyze and fix timing paths, including crosstalk and noise analysis.
What they ask for
- Hands-on experience with full-chip/sub-chip Static Timing Analysis (STA), timing convergence, and timing constraint generation and management.
- Expertise in timing-path analysis and fixes through ECOs, including crosstalk and noise analysis.
- Experience in physical design and optimization, and knowledge of industry-standard STA and timing convergence tools.
- Knowledge of deep sub-micron process nodes and hands-on experience modeling and converging timing in these nodes.
Nice to have
- Background in domain-specific STA and timing convergence for GPUs, CPUs, LPUs, or SoCs; logic synthesis and equivalence checking/FV.
- Understanding of DFT timing closure or digital logic/macros in AMS designs/IPs; methodology, flow development, or automation experience.
Pay
136,000 USD - 218,500 USD base salary (Level 3); 168,000 USD - 264,500 USD base salary (Level 4)
Tools
Static Timing Analysis (STA), ECOs, synthesis, placement, routing, logic restructuring, DFT, BIST
AI focus
The role focuses on ASIC timing engineering; the posting states that NVIDIA uses AI tools in its recruiting processes, not that the job involves AI work.
Model-written summary · the original posting is authoritative