NVIDIA
Senior ASIC Verification Engineer
$136K–$264K
US, CA, Santa Clara +4 · Senior · Full-time · Posted Oct 5, 2026
- Location
- US, CA, Santa Clara
US, TX, Austin
US, OR, Remote
US, WA, Remote
US, CA, Remote - Experience
- 5+ years of relevant industry work experience.
- Education
- BS or MS in EE/ECE or equivalent experience.
About the job
Validates clocking and reset logic for NVIDIA Tegra and GPU products, from verification planning and automation through execution, coverage, bug resolution, and productization.
What you'll do
- Own end-to-end validation of clocking structures, including test plans, flows, coverage, test execution, and bug identification and resolution.
- Develop scalable verification solutions and use industry-standard methodologies and tools.
- Partner with architecture and design teams and coordinate across internal and external groups.
What they ask for
- BS or MS in EE/ECE, or equivalent experience.
- Good understanding of Logic Design and Architecture.
- Expertise in verification flows such as SV constraint random verification, UVM, Formal Verification, and coverage metrics.
- Strong coding skills in System Verilog, scripting languages (Perl/python), and C++; experience with pre-silicon test plans and block- and system-level verification.
Nice to have
- Previous experience automating design verification tasks or using object-oriented programming.
- Prior IP or block-level design/verification experience, methodology development, or driving projects to completion.
Pay
136,000 USD - 218,500 USD (base salary, Level 3); 168,000 USD - 264,500 USD (base salary, Level 4)
Tools
System Verilog, UVM, C++, Perl, Python, NVIDIA custom compilers and tools
AI focus
Verifies clocking and reset logic for product lines that include artificial intelligence applications; no direct AI development work is stated.
Model-written summary · the original posting is authoritative