NVIDIA
Senior Cache Coherency Architect
$152K–$288K
US, CA, Santa Clara · Senior · Full-time · Posted Apr 20, 2026
- Experience
- 5+ years in processor design or other high-performance semiconductor designs.
- Education
- Master’s degree in electrical engineering, Computer Engineering, Computer Science, or equivalent experience.
About the job
Architects, models, and supports implementation of cache-coherent interconnects and cache subsystems for NVIDIA SoC products.
What you'll do
- Define interconnect architecture, cache-coherency protocols, and on-chip interfaces; specify and integrate interconnect IP.
- Develop functional and performance models and work with design and verification teams to validate implementations against architectural specifications and PPA requirements.
- Support silicon bring-up and post-silicon debug.
What they ask for
- Master’s degree in electrical engineering, Computer Engineering, Computer Science, or equivalent experience.
- 5+ years of experience in processor design or other high-performance semiconductor designs.
- Deep cache-coherency knowledge and hands-on experience with industry-standard protocols; experience authoring specifications and designing cache-coherent interconnects.
- Experience developing coherent IP models (e.g., VIPs, BFMs) and proficiency in C, C++, Python, and Verilog.
Pay
152,000 USD - 241,500 USD (base salary); 184,000 USD - 287,500 USD (base salary)
Tools
AXI, ACE, CHI, C, C++, Python, Verilog
Model-written summary · the original posting is authoritative