NVIDIA
Senior Circuit Timing Engineer
$168K–$310K
US, CA, Santa Clara +1 · Senior · Full-time · Posted Oct 11, 2026
- Location
- US, CA, Santa Clara
US, CA, Remote - Experience
- 6+ years of digital circuit design experience for Masters; 8+ years for Bachelors.
- Education
- BSEE/MS preferred in Electrical, Computer Engineering or equivalent experience.
About the job
Design and sign off timing for custom processor circuit macros, developing timing models and methodologies while improving power, performance, area, and reliability.
What you'll do
- Design circuits for hardware security, adaptive clocking, and power management; deliver transistor-level designs, schematics, and layouts.
- Analyze and validate timing using STA and SPICE tools; develop timing models and support timing signoff, closure, and ECOs.
- Collaborate across teams on timing constraints, timing and power convergence, DFT, and AI/ML integration into design methods.
What they ask for
- Excellent understanding of deep submicron process issues and digital circuit design techniques.
- Expertise with industry-standard STA tools, including Nanotime, Primetime, and Tempus.
- Hands-on experience with Spice simulations, EM/IR analysis, and static timing analysis/closure.
- Proven experience generating and managing timing constraints.
Nice to have
- Hands-on experience designing and analyzing low-power circuits.
- Experience across the silicon design flow, post-silicon characterization and debug, or timing closure for AMS designs/IPs.
Pay
168,000 USD - 264,500 USD base salary (Level 4); 196,000 USD - 310,500 USD base salary (Level 5)
Tools
Nanotime, PrimeTime, Tempus, SPICE, EM/IR, .libs, STA, PVerf
AI focus
Integrate AI/ML techniques into the design process and methodology. NVIDIA also states that it uses AI tools in recruiting.
Model-written summary · the original posting is authoritative