Senior Design Verification Engineer - GPU Memory Subsystem

What you'll do

• Develop and implement verification strategies for GPU ASIC memory subsystem IP with RTL, DV, FV, and architecture teams.
• Perform functional and performance verification using advanced tools and methodologies.
• Build understanding of the IP’s microarchitecture and implementation while advancing verification skills.

What they ask for

• BS degree in CompE, EE, CS, or equivalent experience.
• 5+ years covering the full scope of pre-silicon ASIC verification, including verification strategy, test plans, tests, testbench components, regression triage, debug, and coverage closure.
• Experience with industry-standard tools.
• Working knowledge of computer architecture fundamentals and constructs in Verilog/System Verilog.

Nice to have

• Experience with caches, coherency, complex pipelines, arbiters, or interconnect networks; infrastructure development or reusable UVM testbench components.
• Strong analytical and debug skills; Python or C++ programming/scripting, including suitable algorithms, data structures, and error handling; use of AI to support design and verification development.

Pay

136,000 USD - 218,500 USD (base salary, Level 3); 168,000 USD - 264,500 USD (base salary, Level 4)

Tools

Verilog, System Verilog, Python, C++, UVM

AI focus

Preferred use of AI to support design and verification development. NVIDIA uses AI tools in its recruiting processes.