NVIDIA
Senior DFT Engineer
$136K–$264K
US, CA, Santa Clara · Senior · Full-time · Posted Oct 7, 2026
- Experience
- 5+ years with BSEE or equivalent experience; 3+ years with MSEE; or PhD in DFT or related domains.
- Education
- BSEE (or equivalent experience), MSEE, or PhD in DFT or related domains.
About the job
Leads design and implementation of design-for-test methodologies and chip bring-up from pre-silicon through production, supporting silicon quality and test execution.
What you'll do
- Design and deploy test methodologies, including test access mechanisms, IO BIST, memory BIST, and scan compression.
- Plan and execute chip bring-up; develop reusable processes and workflows and collaborate with VLSI and Product Engineering.
- Mentor junior engineers and improve cross-team communication and handoffs.
What they ask for
- BSEE or equivalent experience with 5+ years, MSEE with 3+ years, or PhD in DFT or related domains.
- Knowledge of scan test plans, BIST for memories and IOs, fault modeling, ATPG, and fault simulation.
- Experience validating test patterns and logic on complex, multi-million gate builds using vendor tools; silicon debug and bring-up experience.
- Strong programming and scripting skills; excellent written and oral communication skills.
Nice to have
- Deep DFT architecture knowledge; direct GPU/SoC bring-up and hands-on lab validation.
- Knowledge of InSystem Test, PVT dependencies, VF characterization, fault models, DPPM, quality metrics, or RAS.
Pay
136,000 USD - 218,500 USD base salary (Level 3); 168,000 USD - 264,500 USD base salary (Level 4)
Tools
IO BIST, memory BIST, scan compression, ATPG, oscilloscopes, logic analyzers
AI focus
NVIDIA uses AI tools in its recruiting processes; the role’s AI work is not stated.
Model-written summary · the original posting is authoritative