NVIDIA
Senior DFT Engineer
$168K–$310K
US, CA, Santa Clara +1 · Senior · Full-time · Posted Oct 2, 2026
- Location
- US, CA, Santa Clara
US, TX, Austin - Experience
- 6+ years of hands-on DFT experience.
- Education
- MS/PhD or equivalent experience in Electrical Engineering or a related field.
About the job
Develops and deploys design-for-test architectures and methodologies for NVIDIA silicon, owning the ATPG lifecycle from verification through ATE bring-up.
What you'll do
- Develop test methodologies and co-architect DFT strategies for next-generation silicon.
- Own ATPG verification, coverage analysis, pattern generation, and ATE bring-up.
- Collaborate with EDA vendors and internal teams; mentor junior engineers.
What they ask for
- MS/PhD or equivalent experience in Electrical Engineering or a related field
- 6+ years of hands-on experience in Design-For-Test (DFT)
- Deep knowledge of DFT tools, methodologies, and test strategies for complex, large-scale designs
- Strong experience with industry standard ATPG tools
Nice to have
- Experience with 2.5D/3D ICs, multi-chiplet architectures, or reticle-sized designs
- Background in developing or enhancing EDA tool flows; experience with Silicon testing and Automatic Test Equipment (ATE)
Pay
168,000 USD - 264,500 USD base salary (Level 4); 196,000 USD - 310,500 USD base salary (Level 5)
Tools
ATPG, EDA, ATE, DFT
AI focus
AI is mentioned as a preferred automation capability; NVIDIA also states it uses AI tools in its recruiting processes.
Model-written summary · the original posting is authoritative